An analog controlled phase-locked loop (PLL) circuit detects the phase difference between a reference clock and an output clock of a voltage controlled oscillator (VCO), as the width of the output pulse by a phase comparator. Further, the PLL circuit converts the voltage through a loop filter configured such that the output of the phase comparator has desired PLL characteristics. The PLL circuit applies the converted voltage to a control voltage terminal of the VCO, and controls the frequency of the VCO output clock.
Such an analog controlled PLL circuit requires a resistive element and a capacitive element for the loop filter configured to obtain desired PLL characteristics. However, implementation of these elements in a typical CMOS process is difficult in terms of size and constant accuracy. Thus, the resistive and capacitive elements are often externally mounted through pins of the device. For this reason, miniaturization of the process does not necessarily contribute to miniaturization of the circuit.
Further, when desired PLL characteristics are limited, initial fluctuations of the constants of the externally mounted resistive and capacitive elements as well as temperature changes are a problem. In addition, there is an increased demand for high functionality of the PLL circuit, such as (1) the switching function for switching plural reference clocks input thereto, and (2) the so-called hold-over function for ensuring the output phase of the PLL circuit for a certain period of time when the reference clock is interrupted. As a result, the achievement of desired characteristics is often difficult in the analog controlled PLL circuit.
Thus, in recent years, the analog controlled PLL circuits have been replaced with PLL circuits in which the phase comparator and the loop filter are digitally controlled. The digitally controlled PLL circuit requires a digital phase detector for outputting the phase difference between two clocks, a reference clock and a VCO output clock, as a digital value. The detection accuracy of the phase difference of the digital phase detector is a key factor for the PLL characteristics. It is therefore important to increase the accuracy of the digital phase detector.
To solve this problem, there has been proposed a digital phase detector for quantizing and detecting the phase difference by the delay time of an inverter serving as a delay element, and converts the quantized data to a digital value (see JP-A No. 076886/2002 or JP-A No. 110370/2007).
Now, a conventional digital phase detector will be described with reference to FIGS. 1 and 2. Here, FIG. 1 is a block diagram of a digital phase detector. FIG. 2 is a time chart of the digital phase detector.
In FIG. 1, a digital phase detector 700 includes n inverters 701 serving as delay elements, and n flip flops (hereinafter referred to as F/Fs) 702. A clock CLKi (an input clock signal) is sequentially delayed by n series-connected inverters 701. Outputs D (0) to D(n−1) of the inverters 701 are input to the F/Fs 702, respectively. The F/Fs 702 latch the outputs D(0) to D(n−1) of the inverters 701 by a clock CLKr (a reference clock signal), and output Q (0:n−1), respectively.
The timing of the digital phase detector 700 with n=8, will be described with reference to FIG. 2. In FIG. 2, the abscissa represents the time, and the ordinate represents, from the top to the bottom, (a) CLKi, (b) D (0), (c) D (1), (d) D (2), (e) D (3), (f) D (4), (g) D (5), (h) D (6), (i) D (7), (j) CLKr, (k) Q (0:7). D (0) to D (7) are generated by delaying the clock CLKi by a delay time ΔT through the inverters 701 serving as delay elements. In the time chart of FIG. 2, D(0) to D(7) are latched at the timing of the rising edge of the clock CLKr to obtain Q (0:7)=“11100000”.
Because the obtained values vary depending on the phase position of the clock CLKi with respect to the clock CLKr, Q (0:7) obtained as described above shows a digital value indicating the phase difference between the clock CLKr and the clock CLKi. In this way, the digital phase detector 700 can quantize the phase difference between the clock CLKr and the clock CLKi per unit time of the delay time ΔT of the inverter 701, and convert to a digital value. Further, because the phase difference between the clock CLKr and the clock CLKi is quantized by the delay time ΔT of the inverter 701, the digital phase detector 700 can detect the phase difference with an accuracy of ΔT.
However, the above described digital phase detector has the following problems.
First, the delay time of the inverter used in the digital phase detector 700 varies depending on the CMOS device implementing the digital phase detector. In other words, the detection accuracy of the phase difference of the digital phase detector is dependent on the CMOS device. For this reason, it is necessary to verify that the desired PLL characteristics can be achieved for each CMOS device implementing the digital phase detector.
Second, the delay time of the inverter 701 used in the digital phase detector 700 varies due to fluctuations in process and changes in source voltage and temperature. As a result, this affects the detection accuracy of the phase difference. For this reason, it is necessary to suppress such fluctuations as much as possible to ensure the desired detection accuracy.
Third, to keep the phase difference detection accuracy to ΔT in the digital phase detector 700, it is necessary to consider the delay time of the wiring between the inverters 701, and the delay time of the wiring from each inverter 701 to each F/F 702, in addition to the delay time of each of the inverters serving as delay elements. For this reason, both the layout and wiring of the inverters and F/Fs should be fixed.
For application specific standard products (ASSPs), the layout and wiring of inverters and F/Fs can be fixed specific to the desired PLL circuit characteristics and the implementing device. However, it is not efficient for devices that can implement user logic, such as a gate array or field programmable gate array (FPGA), to fix the layout and wiring of the inverters 701 and F/Fs for each user logic design. Basically, products with fixed layout and wiring should be provided by device venders as hard macro. However, the desired PLL circuit characteristics differ depending on the application of each user, so that in general the inverters and F/Fs are not often provided as hard macro.
Thus, it has been difficult to realize the digital phase detector 700 in a device that can implement user logic such as a gate array or FPGA.